VHDL Basit Bir İşlemci Kodu

İki portu olan verilen komutlara göre giriş portundaki data direk olarak diğer porta aktaran veya verilen iki datayı toplayarak aktaran aşağıdaki özelliklerde basit bir işlemci tasarlayınız. İşlemcinin giriş ve çıkışlarında 16×16 (16 bit veri yolu 16 bit derinlik)’lik FIFO’lar bulunacaktır. Girdi portundan işlemciye iki tür komut yazılabilecektir.
1. Komut tipi : Bu komutun ilk 8 biti komut (AA Hex), ikinci 8 biti datadır. Bu komut yazıldığında
datayı karşı taraftaki FIFO’ya yazacaktır.
2. Komut tipi : Bu komutun ilk 8 biti komut (55 Hex), daha sonra gelen ilk 4 bit data-1 ikinci 4 bit
data-2’dir. Bu komut yazıldığında data-1 ve data-2’yi toplayacak, toplamı 8 bit olarak komutun
sonunda ekleyerek karşı taraftaki FIFO’ya yazacaktır.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FPU is
    Port ( DIN : in STD_LOGIC_VECTOR (15 downto 0);
           DOUT : out STD_LOGIC_VECTOR (15 downto 0);
           WE : in STD_LOGIC;
           WR_CLK : in STD_LOGIC;
           RD : in STD_LOGIC;
           RD_CLK : in STD_LOGIC);
end FPU;

architecture Behavioral of FPU is
    COMPONENT fifo_gen
      PORT (
        rst : IN STD_LOGIC;
        wr_clk : IN STD_LOGIC;
        rd_clk : IN STD_LOGIC;
        din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
        wr_en : IN STD_LOGIC;
        rd_en : IN STD_LOGIC;
        dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
        full : OUT STD_LOGIC;
        empty : OUT STD_LOGIC
      );
    END COMPONENT;
    COMPONENT FPU_ADD is
        Port ( S1 : in STD_LOGIC_VECTOR (3 downto 0);
               S2 : in STD_LOGIC_VECTOR (3 downto 0);
               DOUT : out STD_LOGIC_VECTOR (7 downto 0));
    end COMPONENT;
    COMPONENT FPU_MUX is
        Port ( S1 : in STD_LOGIC_VECTOR (7 downto 0);
               S2 : in STD_LOGIC_VECTOR (7 downto 0);
               C : in STD_LOGIC;
               DOUT : out STD_LOGIC_VECTOR (7 downto 0));
    end COMPONENT;
    COMPONENT FPU_CORE is
        Port ( DIN : in STD_LOGIC_VECTOR (7 downto 0);
               C : out STD_LOGIC := '1';
               fifoINempty : in STD_LOGIC;
               fifoOUTempty : in STD_LOGIC;
               WR_CLK : in STD_LOGIC;
               RD_CLK : in STD_LOGIC;        
               rdIN : out STD_LOGIC;
               weOUT : out STD_LOGIC);
    end COMPONENT;
    Signal fifoINfull, fifoOUTfull : STD_LOGIC;
    Signal fifoINempty, fifoOUTempty : STD_LOGIC;
    Signal muxC : STD_LOGIC;
    Signal mux1, mux2, addOUT, muxOUT : STD_LOGIC_VECTOR(7 downto 0);
    Signal add1, add2 : STD_LOGIC_VECTOR(3 downto 0);
    Signal fifoINout, fifoOUTin : STD_LOGIC_VECTOR(15 downto 0);
    Signal rdIN, weOUT : STD_LOGIC;
begin

    add1 <= fifoINout(3 downto 0);
    add2 <= fifoINout(7 downto 4);
    mux1 <= fifoINout(7 downto 0);
    mux2 <= addOUT;
    fifoOUTin <= fifoINout(15 downto 8) & muxOUT;

    FIFO_IN : fifo_gen port map(
        rst => '0',
        wr_clk => WR_CLK,
        rd_clk => RD_CLK,
        din => DIN,
        wr_en => WE,
        rd_en => rdIN,
        dout => fifoINout,
        full => fifoINfull,
        empty => fifoINempty);
    FIFO_OUT : fifo_gen port map(
        rst => '0',
        wr_clk => WR_CLK,
        rd_clk => RD_CLK,
        din => fifoOUTin,
        wr_en => weOUT,
        rd_en => RD,
        dout => DOUT,
        full => fifoOUTfull,
        empty => fifoOUTempty);
    ADD : FPU_ADD port map(
        S1 => add1,
        S2 => add2,
        DOUT => addOUT);
    MUX : FPU_MUX port map(
        S1 => mux1,
        S2 => mux2,
        C => muxC,
        DOUT => muxOUT);
    CORE : FPU_CORE  port map(
        DIN => fifoINout(15 downto 8),
        C => muxC,
        fifoINempty => fifoINempty,
        fifoOUTempty => fifoOUTempty, 
        WR_CLK => WR_CLK,
        RD_CLK => RD_CLK,          
        rdIN => rdIN,
        weOUT => weOUT);

end Behavioral;

Kullanılan alt bloklar

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FPU_ADD is
    Port ( S1 : in STD_LOGIC_VECTOR (3 downto 0);
           S2 : in STD_LOGIC_VECTOR (3 downto 0);
           DOUT : out STD_LOGIC_VECTOR (7 downto 0));
end FPU_ADD;

architecture Behavioral of FPU_ADD is
begin
    DOUT <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(S1) + CONV_INTEGER(S2), 8);
end Behavioral;

entity FPU_CORE is
    Port ( DIN : in STD_LOGIC_VECTOR (7 downto 0);
           C : out STD_LOGIC := '1';
           fifoINempty : in STD_LOGIC;
           fifoOUTempty : in STD_LOGIC;   
           WR_CLK : in STD_LOGIC;
           RD_CLK : in STD_LOGIC;            
           rdIN : out STD_LOGIC := '0';
           weOUT : out STD_LOGIC := '0');
end FPU_CORE;

architecture Behavioral of FPU_CORE is
    Signal weIN, rdOUT, SR : STD_LOGIC := '0';
begin
    with fifoINempty select rdIN <=
        '1' when '0',
        '0' when '1',
        '0' when others;
        
    process (WR_CLK) begin
        if rising_edge(WR_CLK) then
            weOUT <= SR;      
        end if;
    end process;
    
    with fifoINempty select SR <=
        '1' when '0',
        '0' when '1',
        '0' when others;

    with DIN select C <=
        '0' when X"AA",
        '1' when X"55",
        '0' when others;
        
end Behavioral;

entity FPU_MUX is
    Port ( S1 : in STD_LOGIC_VECTOR (7 downto 0);
           S2 : in STD_LOGIC_VECTOR (7 downto 0);
           C : in STD_LOGIC;
           DOUT : out STD_LOGIC_VECTOR (7 downto 0));
end FPU_MUX;

architecture Behavioral of FPU_MUX is

begin
    with C select DOUT <=
        S2 when '1',
        S1 when '0',
        X"00" when others;
        
end Behavioral;